参考设计
(13)
PMP20026 TPS53515 Low Power DDR Memory Power Supply Reference Design | TI.com
PMP20026: The PMP20026 reference design provides an efficient low power solution for DDR4 memory. The power supply is powered from a 12V source and regulates the output to 1.2V at up to 6A. The TPS53515 operates in a single phase buck mode at 500kHz that allows for very high efficiency conversion. The solution size is25mm x 15mm. The peak effciency approaches 90% at 5A. At very light loads the efficiency is still above 40%.
High Power Density 12Vin, 11.8W Buck Converter with Inductor On Top of the IC
TIDA-00595: The TPS53515 Inductor-On-Top Step-Down Buck Converter reference design enables reduction of X-Y area while enabling >87% efficiency with 2.6W of power loss @12A load and 12mV of output voltage ripple with only 10x22uF ceramic output caps. This power reference design supports a 12V input and a 1.2V output at 12A and switches at 1MHz.
PMP9475 Xilinx Virtex UltraScale FPGA Power Solution with PMBus Reference Design | TI.com
PMP9475: The PMP9475 12V-input reference design provides all the power supply rails necessary to power Xilinx's Virtex® UltraScale™ family of FPGAs in a compact, highly efficient design. This design uses several of TI's PMBus Point-Of-Load voltage regulators for ease of design/configuration and telemetry of critical rails. It features a UCD90120A for flexible power up and power down sequencing as well as voltage monitoring, current monitoring, and voltage margining through the PMBus interface.
Xilinx Virtex UltraScale FPGA Power Solution with PMBus Reference Design
PMP9475: The PMP9475 12V-input reference design provides all the power supply rails necessary to power Xilinx's Virtex® UltraScale™ family of FPGAs in a compact, highly efficient design. This design uses several of TI's PMBus Point-Of-Load voltage regulators for ease of design/configuration and telemetry of critical rails. It features a UCD90120A for flexible power up and power down sequencing as well as voltage monitoring, current monitoring, and voltage margining through the PMBus interface.
