参考设计
(14)
Ethernet Bootloader for Microcontroller
TIDM-ETHERNET-BOOTLOADER: This design describes how to use Ethernet module to transfer the firmware image and program it into flash on Hercules MCU. The Ethernet bootloader is based on TFTP (Trivial File Transfer Protocol) which is a file transfer protocol notable for its simplicity. And it is a small piece of code that can be programmed at the beginning of the flash to act as an application loader as well as an update mechanism for applications running on a Hercules microcontroller.
Altera Arria V GZ FPGA Discrete Power Solution Reference Design
PMP9357: The PMP9357 reference design is a complete power solution for Altera's Arria V series FPGAs. This design uses several TPS54620 synchronous step down converters, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. To provide correct power sequencing, a UCD90120A power supply sequencer/monitor is used and can be controlled through I2C.
Altera Arria V GX FPGA Power Solution Reference Design
PMP9449: The PMP9449 reference design provides all the power supply rails necessary to power Altera's Arria® V GX family of FPGAs. It utilizes a TPS38600 to monitor the input supply and provide power on sequencing. This design features low cost, small footprint discrete ICs and is powered from a single 5V input.
Dual-channel XAUI to SFI Reference Design for Systems with Two or More SFP+ Optical Ports
TIDA-00234: The TIDA-00234 XAUI to SFI reference design is intended for Enterprise and Service Provider Networking applications like Ethernet Switches and Routers that implement multiple 10G Ethernet compliant Optical (SFP+) ports. This reference design features the TLK10232 device which is the most compact Dual-channel XAUI-to-SFI Transceiver with the lowest power consumption in its category. This reference design allows access to the high-speed signals (up to 10Gbps) generated by the TLK10232 via SMA connectors or an SFP+ Module via the SFP+ optical module cage. Also, featured is the CDCM6208 device that can provide extremely low-jitter Clock input to the TLK10232 in customer systems that do not have one available (or does not meet the jitter requirement of the system).
DisplayPort Video 4:1 Aggregation Reference Design
TIDA-00309: This verified reference design is a complete four channel DisplayPort aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous DisplayPort (DP) sources together into one 10.8 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is used to de-aggregate and seamlessly redisplay the original video content.
Synchronizing Multiple JESD204B ADCs for Emitter Position Location Reference Design
TIDA-00467: A common technique to estimate the position of emitters uses the amplitude and phase shift data of a signal derived from an array of spatially distributed sensors. For such systems, it is important to guarantee a deterministic phase relationship between the sensors to minimize errors in the actual measured data. This application design will discuss how multiple Analog to Digital Converters (ADCs) with a JESD204B interface can be synchronized so that the sampled data from the ADCs are phase aligned.
