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首页 > 电子元器件选型 > 二极管 > 整流二极管

MBRS540T3G

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MBRS540T3G
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ON Semiconductor

Schottky Power Rectifier, Surface Mount, 5.0 A, 40 V, SMC, 2500-REEL

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¥4.5457
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375,492
生命周期状态: Active
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MBRS540T3G ON Semiconductor 也适用于 MBRS540 ,MBRS540T3G ,MBRS540T3 等其余1个型号

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RF Sampling 4-GSPS ADC Reference Design with 8-GHz DC-Coupled Differential Amplifier
TIDA-00431: Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies. This reference design describes a wideband RF receiver utilizing a 4-GSPS analog-to-digital converter (ADC), with an 8-GHz, DC-coupled, fully differential amplifier front end. The amplifier front end provides signal gain and allows capture of signals down to DC, which is not possible with a balun-coupled input.
Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems
TIDA-00432: This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown for each EVM. The FPGA firmware is described and the relevant Xilinx IP block configuration parameters are shown. Data taken on the actual hardware is shown and analyzed, showing synchronization within 50 ps without characterized cables or calibrated propagation delays.
Complete PMBus Power System for Enterprise Ethernet Switches Reference Design
PMP10896: Complete PMBus power system for 3 ASIC/FPGA cores, DDR3 core memory, and auxiliary voltages found on high-performance Ethernet Switches.
Clocking Solution Reference Design for GSPS ADCs
TIDA-00359: Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and SFDR performance.
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