参考设计
(40)
Xilinx® Zynq® 7000 series (XC7Z015) Power Solution, 8W - Reference Design
PMP10601.1: The PMP10601 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015) FPGA. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
Altera Arria V SoC Power Supply Reference Design
PMP9360.6: This reference design provides all the power supply rails necessary to power Altera's Arria V SoC FPGA. This design uses LMZ3 series modules to generate the rails to power the FPGA.
Altera Arria V SoC Power Supply Reference Design
PMP9360.4: This reference design provides all the power supply rails necessary to power Altera's Arria V SoC FPGA. This design uses LMZ3 series modules to generate the rails to power the FPGA.
Xilinx® Zynq® 7000 series (XC7Z015) Power Solution, 8W - Reference Design
PMP10601.2: The PMP10601 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015) FPGA. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
Altera Arria V SoC Power Supply Reference Design
PMP9360.5: This reference design provides all the power supply rails necessary to power Altera's Arria V SoC FPGA. This design uses LMZ3 series modules to generate the rails to power the FPGA.
Xilinx(r) Ultrascale(r) 16nm FPGA/SoC Power Solution for Mobile Radio Basestation with PMBus
PMP10555: The PMP10555 reference design provides all the power supply rails necessary to power Xilinx® Ultrascale® 16nm family of FPGAs/SoCs in a mobile radio basestation application. This design uses a PMBus compatible 20A integrated FET buck converter for the core and two multi-output buck regulator ICs to provide the remaining supplies necessary rails to power the FPGA. It also features two LM3880's for flexible power up and power down sequencing. This design uses a 12V input.
16.8V/18A 4 Switch Buck Boost Reference Design
PMP10214: The PMP10214 reference design has a wide input voltage range from 8 -16V DC with a surge capapbility to 40V. The topology is 4 switch buck boost. It is best suited for charging 4s Li-Ion starter batteries (4 cells).
Altera Arria V SoC Power Supply Reference Design
PMP9360.3: This reference design provides all the power supply rails necessary to power Altera's Arria V SoC FPGA. This design uses LMZ3 series modules to generate the rails to power the FPGA.
Altera Arria V SoC Power Supply Reference Design
PMP9360.2: This reference design provides all the power supply rails necessary to power Altera's Arria V SoC FPGA. This design uses LMZ3 series modules to generate the rails to power the FPGA.
Xilinx Kintex UltraScale FPGA Power Solution Reference Design with PMBus
PMP9444: The PMP9444 reference design provides all the power supply rails necessary to power Xilinx's Kintex UltraScale family of FPGAs. It features two UCD90120A's for flexible power up and power down sequencing as well as voltage monitoring, current monitoring, and voltage margining through the PMBus interface. This design uses a 12V input.
Xilinx® Zynq®7000 series (XC7Z015) Power Solution, 5W - Reference Design
PMP10600.2: The PMP10600.2 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015) FPGA. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
16-bit 400KSPS 4-Ch. Multiplexed Data Acquisition Ref Design for High Voltage Inputs, Low Distortion
TIPD151: This TI Verified Design implements a 16-bit, differential 4-channel multiplexed data acquisition system at 400KSPS throughput for high voltage differential input of ±20 V (40 Vpk-pk) industrial applications. The circuit is realized with a 16-bit successive-approximation-resistor (SAR) analog-to-digital converter (ADC), a precision high voltage signal conditioning front end, and a 4-channel differential multiplexer (MUX). The design details the process for optimizing the precision high voltage front end drive circuit using the OPA192 and OPA140 to achieve excellent dynamic performance with the ADS8864.
Xilinx Zynq 7000 Series (XC7Z045) 20W Reference Design
PMP10613.2: The PMP10613 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z045) FPGA. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
Xilinx Zynq 7000 Series (XC7Z045) 20W Reference Design
PMP10613.1: The PMP10613 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z045) FPGA. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
Altera® Stratix® V FPGA Power Solution
PMP9365: The PMP9365 reference design provides all the power supply rails necessary to power Altera's Stratix V family of FPGAs. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. It also features two LM3880's for flexible power up and power down sequencing. This design uses a 12V input.
Altera Arria V SoC Power Supply Reference Design
PMP9360.1: This reference design provides all the power supply rails necessary to power Altera's Arria V SoC FPGA. This design uses LMZ3 series modules to generate the rails to power the FPGA.
Altera Cyclone V SoC FPGA Power Reference Design
PMP9353: The PMP9353 reference design is a complete power solution for Altera Cyclone V SoC devices. This design uses several LMZ3 series modules , two LDOs, and a DDR termination regulator to provide all the necessary rails to power the SoC chip. This design also shows correct power-up sequencing.
Xilinx® Zynq®7000 series (XC7Z015) Power Solution, 5W - Reference Design
PMP10600.1: The PMP10600.1 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015) FPGA. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
Altera Arria V SoC FPGA Power Solution Reference Design
PMP9360: The PMP9360 reference design is a complete power solution for Altera's Arria V™ SoC devices. This design uses several LMZ3 series modules , an LDO, and a DDR termination regulator to provide all the necessary rails to power the SoC chip. This design also shows correct power up sequencing.
Altera Arria V SoC Power Supply Reference Design
PMP9360.7: This reference design provides all the power supply rails necessary to power Altera's Arria V SoC FPGA. This design uses LMZ3 series modules to generate the rails to power the FPGA.
Xilinx Zynq 7000 Series (XC7Z045) 20W Reference Design - PMP10613.1 - TI Tool Folder
PMP10613: The PMP10613 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z045) FPGA. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
Xilinx Virtex UltraScale FPGA Power Solution with PMBus Reference Design
PMP9475: The PMP9475 12V-input reference design provides all the power supply rails necessary to power Xilinx's Virtex® UltraScale™ family of FPGAs in a compact, highly efficient design. This design uses several of TI's PMBus Point-Of-Load voltage regulators for ease of design/configuration and telemetry of critical rails. It features a UCD90120A for flexible power up and power down sequencing as well as voltage monitoring, current monitoring, and voltage margining through the PMBus interface.
