93LC46B-I/SN中文资料_PDF数据手册

93LC46B-I/SN

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Microchip Technology Inc

64 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8

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详细参数

Source Content uid

93LC46B-I/SN

不含铅

符合

Active

SOIC

compliant

EAR99

8542.32.00.51

4 weeks

3266

0.53

2 MHz

200

R-PDSO-G8

4.9 mm

1024 bit

EEPROM

64 words

SYNCHRONOUS

85 °C

-40 °C

64X16

TOTEM POLE

PLASTIC/EPOXY

SOP

SOP8,.25

RECTANGULAR

SMALL OUTLINE

SERIAL

260

Not Qualified

YES

TS 16949

1.75 mm

MICROWIRE

0.000001 A

0.002 mA

5.5 V

2.5 V

3 V

YES

CMOS

INDUSTRIAL

MATTE TIN

GULL WING

1.27 mm

DUAL

3.9 mm

6 ms

SOFTWARE

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93AA46 Microchip Technology Inc 也适用于 93AA46BT-I/SNG ,93LC46B-I/PG ,93AA46B-I/SNG 等其余

参考设计

(3)

Altera Arria V GX FPGA Power Solution Reference Design

PMP9449: The PMP9449 reference design provides all the power supply rails necessary to power Altera's Arria® V GX family of FPGAs. It utilizes a TPS38600 to monitor the input supply and provide power on sequencing. This design features low cost, small footprint discrete ICs and is powered from a single 5V input.

FPGA Firmware Project for Measuring Bit Errors in the Output Word of an A to D Converter

TIDA-00070: For applications where there are bit errors and resulting sample errors (also called sparkle codes, word errors, or code errors), the ability to measure the Error rates caused by these bit errors is important. This FPGA firmware based application note proposes a method to accurately measure these errors over an indefinite time and provides an example of how this measurement can be done using a simple FPGA platform. Code is available on request for the two examples described in the application note.

Synchronizing Multiple JESD204B ADCs for Emitter Position Location Reference Design

TIDA-00467: A common technique to estimate the position of emitters uses the amplitude and phase shift data of a signal derived from an array of spatially distributed sensors. For such systems, it is important to guarantee a deterministic phase relationship between the sensors to minimize errors in the actual measured data. This application design will discuss how multiple Analog to Digital Converters (ADCs) with a JESD204B interface can be synchronized so that the sampled data from the ADCs are phase aligned.

< / 共 3 个参考设计 >

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